CMOS circuits are commonly designed for a permissible voltage range of only 5 volts. The technological manufacturing parameters and the geometrical design rules of the individual regions are optimized for this voltage range. However, there are applications for CMOS circuits which lie outside this usual 5 V supply and in which the cost of a separate, stable 5 V supply network would be prohibitive. Such applications are, for example, spatially separated circuits for electronic transducers, sensors, or controllers in industrial or commercial equipment. One important application is the automotive sector with a very unstable on-board system of 12 V or 24 V. It is possible to generate a regulated supply voltage of 5 V on the chip; see, for example, German Patent No. 42 42 989.7-32 to U. Theus and assigned to Deutsche ITT Industries GMBH, the assignee herein. However, this technique increases the amount of chip area required and, hence, the manufacturing costs. In many cases, separate voltage stabilization on the semiconductor chip is not necessary, namely if the circuit itself is relatively insensitive to voltage fluctuations and only few circuit pans require the full breakdown strength.
The following gives a brief survey of the main differences in the breakdown strengths of p- and n-channel transistors. The most critical types are n-channel transistors, whose drain-source breakdown voltage determines the maximum permissible supply voltage. If, however, the heavily n-type doped drain region of the n-channel device is embedded in a lightly doped n-type well for receiving a space-charge region, the maximum permissible drain-source voltage will increase to above 24 V with unchanged manufacturing parameters. A voltage-proof n-channel transistor is thus available.
The p-channel transistor permits a drain-bulk voltage of only -5 V if its channel length is less than 1.2 .mu.m. The maximum permissible drain-bulk voltage increases to at least 12 V if the channel length is greater than 3.75 .mu.m. In the following, the negative sign in the case of the voltage values of the p-channel transistors will be omitted for simplicity, i.e., the values are to be understood as absolute values. If the n-type well (bulk region) of the p-channel transistor is collected to the source electrode, the breakdown strength relates to the drain-source current path in the n-type well. If, on the other hand, the n-type well is connected to another source of potential, the maximum permissible drain-source voltage decreases by the difference in potential between the n-type well and the source electrode.
It is, therefore, the object of the present invention to provide a circuit whereby subcircuits which are at different voltage levels within a CMOS monolithic integrated circuit can be connected together in the simplest possible manner taking into account the desired breakdown strength.